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CPES Patent Information

US Patent: 10032732

Semiconductor Module Arrangement
Christina DiMarino, Dushan Boroyevich, Rolando Burgos, Mark Johnson
Issued: July 24, 2018

In a switching module structure that includes a low-impedance path to ground, such as a parasitic capacitance of an insulating substrate, a further insulating substrate presenting a parasitic capacitance placed in series with the low impedance current path and a connection of a conductive layer to input voltage rails using a single decoupling capacitor or, preferably, a midpoint of the voltage rails formed by a series connection of decoupling capacitos maintains a large portion of common mode (CM) currents which are due to high dV/dt slew rates of SiC and GaN transistors within the switching module.

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