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Hard-Switched Overvoltage Robustness of p-Gate GaN HEMTs at Increasing Temperature
Year: 2021 | Author: Joseph Kozak | Paper: S4.5
Fig. 1. Clamped inductive switching circuit schematic and external parasitic inductance (a), the experimental test circuit that includes the motherboard for the primary power loop and the daughter cards for the minimized gate driver loop and sensing circuitry (b).
Tests were conducted with varying parasitic inductance (LD) values and increasing current values to measure the overvoltage magnitude. The failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. Tests were then repeated with LD = 130 nH but at increasing temperatures (100° C and 150° C). The failures of both devices were consistent with room temperature results and results are shown in Fig. 2. Overall, this work shows the robustness of two commercially available p-Gate GaN HEMTs under overvoltage switching stresses and increasing ambient temperatures.
Fig. 2. Overvoltage failure magnitudes measured at different temperatures for the HD-GIT (a) and SP-HEMT (b).
