CPES SPOTLIGHT
Model of Hysteresis and Magnetoelectric Effect for a Voltage-controllable Inductor
Design of a Compact, Low-inductance, 1200 V 6.5 MΩ SiC Half-bridge Power Module with Flexible Printed Circuit Board Gate-Loop Connection
CPES has presented several papers at ECCE 2019! Please take a look!
CPES has been awarded a new patent: Modular Multilevel Converter Capacitor Voltage Ripple Reduction.
WHAT IS CPES?
We are a research and education center dedicated to creating electric processing systems of the highest value to society. MORE ABOUT CPES
NEWS
Research of Yuhao Zhang's team has been reported by Semiconductor Today!
Yuhao Zhang's work with Vertical gallium oxide Schottky barrier diodes with improved performance
Daniel Kellett will be presenting this months webinar on August 14
Topic: Triangular Current Mode (TCM) Boost Inductor Optimization using 2-D Finite Element Analysis (FEA) and the Improved Generalized Steinmetz Equation (iGSE)