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A High-performance Single-phase Phase-Locked-Loop with Fast Line-voltage Amplitude Tracking
TYPE: PAPER - CONFERENCE
Authors: Boroyevich, Dushan; Cvetkovic, Igor; Dong, Dong; Mattavelli, Paolo
Source: CPES Conference 2011, Blacksburg, VA (April 3-5, 2011)
Pages: D5.5
Publication Date: April 3-5, 2011
Copyright: © Copyright © 2011 CPES. VPI&SU. All rights reserved. Permission is granted to CPES industry members to reproduce all or part of this material for their internal use only.
ABSTRACT
This paper presents a single-phase Phase-Locked-Loop (PLL) system to reject the impact of input voltage amplitude variation. The proposed PLL is based on the unbalanced DQ transformation which doesn't require the generation of orthogonal. Aside from the input phase-angle tracking feedback loop, another peak-voltage detection loop is enclosed to fast track the input signal amplitude, thereby reducing the output second-order harmonic frequency ripple by as much as 80% in most cases. The proposed PLL also allows for the rejection of the dc offset of the input signal, which is thus deemed advantageous due to the ease of implementation, ideal zero steady-state error output, and the offset rejection. Analytical simulation and experimental results are presented for verification purposes.
APPLICATION AREA(S):
- Renewable Energy Systems
TECHNOLOGY AREA(S):
- Modeling and Control
