LIBRARY
Multi-Objective Co-Design Methodology for a High-Density, Medium-Voltage Integrated Power Electronics Building Block
Year: 2023 | Author: Marie Lawson | Paper: H5.9
Fig.1. Co-designed iPEBB module.
The H-bridge component layouts impact converter parasitics, particularly at high frequencies, such that it is critical to analyze their impact on EMC, resonance frequency, and switching performance.
The ODBC power module substrate dielectric layers create capacitive coupling between the switching node and baseplate, causing electromagnetic interference (EMI). A common-mode (CM) screen in the ODBC layers mitigates EMI, at a cost of thermal resistance and increasing the MOSFETs' parasitic capacitances.
The HFT is manufactured around an ungrounded split core with a wide dielectric gap. This limits the achievable range of magnetizing inductances, and also impacts thermal management.
A high switching frequency is desirable for optimal efficiency and power quality. However, this presents a challenge for soft-switching, due to the discharge time required for the switch parasitics (including those augmented by the ODBC and the CM screen).
A model-based approach is used to optimize the iPEBB design. This includes optimizing and validating device physics models (LT Spice) and system behavioral models (PLECS). CLLC investigations typically focus on control, but in this work the thermal, switching, and EMC characteristics of the integrated H-bridges, HFT, and CM screen of the converter are co-designed to identify key tradeoffs and to minimize design cycles. Simulations are used to assess the H-bridges' soft switching performance with the HFT resonant tank, and obtain ranges of acceptable values for the resonant components, the HFT, gating of the CLLC, and the parasitics of the iPEBB layout.
