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Loss Model and Optimization Method for a Switched-Capacitor Divider for a POL Application

Year: 2018 | Author: Owen Jong | Paper: D2.1
Image of switched-capacitor divider.
Fig. 1. 2:1 Switched-capacitor divider.
The new standard architecture utilized by Google drives the industry in pursuit of the best solution for a 48 V to 0.5-2 V point of load (POL) converter. Some research has been done regarding a two-stage approach, where the first stage is a high-efficiency step down converter, and the second stage is a buck converter. This approach achieves high bandwidth, high scalability, and high efficiency. A switch capacitor divider is a promising contender for the first stage. This paper explores a new way to model loss in a switched-capacitor divider circuit, expand it to a higher divider ratio (4:1 and 6:1) switched-capacitor divider circuit, and compare the model with the simulation result. This paper also utilizes the derived models to create a new switched-capacitor divider optimization method based on efficiency versus size trade-offs.

Fig. 1 shows the schematic of a 2:1 switched-capacitor divider. Eq. 1 shows the 2:1 voltage divider rms current based on the ratio of C2/(C1+C3), kn and the normalized time constant of the circuit (τnn = τ/T). The time constant of the circuit is related to the chosen device, and the total capacitance used, in the circuit. This paper finds the model matches closely with the simulation, and the results are within a 5 percent comparative range.

The time constant of a switched-capacitor divider is closely related to the total capacitance used in the circuit. Using this relationship, the tradeoffs between efficiency (conduction loss is the major loss at high load condition) and the total capacitance used for a given device and frequency can be determined, as shown in Fig. 2. By using the same amount of total capacitance, a switched-capacitor divider circuit can achieve higher efficiency by changing the capacitance ratio between C2 and the output capacitors. However, choosing the highest kn is not necessarily desirable. Due to the higher peak on C2 current that may affect the electromagnetic interference performance of the circuit, the noise may get coupled to the output, due to the high peak current, affecting the performance of the processor in POL applications.

Eq. 1.

Image of <i>C<sub>2</sub></i> rms current versus capacitance.
Fig. 2. C2 rms current versus capacitance.

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