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Design of a High-Density Integrated Power Electronics Building Block (iPEBB) Based on 1.7 kV SiC MOSFETs on a Common Substrate

Year: 2021 | Author: Narayan Rajagopal | Paper: S6.3
Topology diagram
Fig. 1. (a) CLLC-based topology for iPEBB, (b) iPEBB design with a top view of the common substrate for the primary side
  A 250-kW, SiC-based integrated power electronics building block (iPEBB) is being explored for applications requiring high-power density. The integrated design features a common substrate, which plays a vital role in the thermal, electrical, and mechanical performance, as well as the weight and reliability of the iPEBB. Silicon nitride (Si3N4) and organic direct bonded copper (ODBC) materials are explored to see their impact on these characteristics and identify key trade-offs. The high-density design is achieved through integrating SiC bridges using 1.7 kV SiC MOSFETs on a common multilayer substrate, which also connects to the high-frequency transformer and other passive components. Compared to employing multiple power modules on a baseplate, the proposed integrated SiC bridges enable smaller power-loop inductance (~3 nH per half-bridge), improved heat dissipation, and lower EMI, while meeting strict weight limitations (<16 kg). Fig. 1(a) shows the iPEBB topology, which enables flexible (dc-dc, dc-ac, ac-dc), galvanically-isolated, bidirectional power conversion. Fig. 1(b) shows the iPEBB primary side components on the common substrate.
  The primary and secondary side of the iPEBB have an identical common substrate, which simplifies manufacturing and reduces cost. This will allow the iPEBB to be mass produced and serve as the backbone of the power distribution system on future electric ships. The iPEBB is intended to be inserted into a rack, which will provide cooling to the top and bottom substrates, and hence the components mounted to them. Thermal, mechanical, and electromagnetic finite element analysis (FEA) simulations were performed to identify suitable substrate materials, dimensions, and layouts, while also minimizing the weight.
  To verify the design, 1.7 kV SiC MOSFET half-bridges with Si3N4 and ODBC substrates have been packaged(Fig. 2(a) and 2(b)). The half-bridges will be tested in a quasi-square wave, zero-voltage switching (QSW-ZVS) buck testbed shown in Fig. 2(c). ZVS reduces the switching losses, enabling the 1.7 kV half-bridges to operate in the hundreds of kilohertz range. The testbed was designed to enable thermal imaging of the SiC MOSFET die during operation. These temperature measurements will be used to verify the thermal models. The proposed design and state- of-the-art substrate materials aid in the realization of the iPEBB, which will advance future electric transportation systems.
  This work was supported by the Office of Naval Research (ONR) with the grant number N00014-16-1-2956.

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