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Reliable Conductor-Semiconductor Interface for High-Temperature Packaging

Fig. 1. Temperature embedded chip module.
One of the inevitable consequences of high temperature power electronics is the much larger temperature excursions (from environmental temperature before turning on, upwards to 200°C or 300°C during operation) and consequently the much larger thermally induced stress excursions on the interfaces between the different materials in eventual integrated modules. These large stresses derive from the mismatch in the coefficients of thermal expansion (CTE) between the different materials in the integrated module. Specifically, power electronics modules need sufficient cross section in the metals (high CTE) used for good electric conduction, exacerbating the mismatch to the low CTE of a high temperature semiconductor such as silicon carbide (SiC). It has for instance been demonstrated that interfaces between the good conductor copper (Cu) and SiC have a very limited lifetime.

This barrier has now been broken by CPES research in high temperature integrated power electronics technology. Hard metals, such as molybdenum (Mo) and chromium (Cr), have an almost perfect match to the CTE of SiC, but have very high electrical resistance and are unsuitable as interconnect metal in power electronics. In a new high temperature packaging technology developed, a composite layer of Cu and Cr is electroplated to solve this problem. Cr is used as a buffer layer between SiC and Cu to reduce the high stress due to mismatch in CTE, and Cu to serve as current carrier. The increase in electrical resistance of this composite layer is negligible, while the mechanical stresses are reduced by half an order of magnitude. Furthermore, the metallized interconnects enables constructing a mechanically balanced structure, finally leading to an order of magnitude reduction in thermally induce mechanical stresses.

The technology has been implemented successfully in a two die-module and operated at 250°C.

Fig. 2. Forward characteristics.
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