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Influence of Phase-Locked Loop on Input Admittance of Three-Phase Voltage Source Converters

Year: 2013
Fig. 1. Influence of PLL on VSC input admittance.
This paper studies the impact of Phase-Locked Loop (PLL) on the input admittance of a three-phase Voltage-Source-Converter (VSC). Two dq domains are defined to analyze the impact of PLL. One is the system dq domain that uses the ac source angle to transform from the abc frame to the dq frame. The other one is the converter dq domain. Converter senses ac source voltage and uses PLL to track the angle of the ac source. The output angle of PLL is used for dq transformation inside the converter. Fig. 1 shows the two dq domains and how perturbation on the ac source voltage propagates to the PLL output angle. From here it moves further to the system abc domain duty ratio and then to the VSC input current in the system dq domain. Fig. 1 indicates that PLL is a bridge that the VSC input voltage perturbation can pass through so that it can introduce perturbation on the input current. The PLL dynamic will then influence the VSC input admittance. To make the analysis of VSC input admittance simple, the transfer function matrices flow chart shown in Fig. 2 is developed to represent the small-signal model of the circuit shown in Fig. 1. Fig. 3 shows the effect of the current loop and the PLL on the VSC input admittance. Clearly, the resonance shown by the open loop admittance is smoothed out by the current loop controller. PLL only affects Ydq and Yqq elements. Changes in the PLL bandwidth only influence the VSC admittance on its Ydq and Yqq elements, where a faster PLL will yield low-er admittances within its bandwidth. The same conclusion still holds when the voltage control loop is closed. Possible instability can happen when different PLL designs are used. In the paper, results for admittances of different PLL designs with current and voltage loop control are shown. Stable and unstable cases caused by PLL are also discussed.

Fig. 2. Transfer function matrix flow chart representation of VSC small signal model including PLL and current feedback control.
Fig. 3. Experimental results of VSC input admittance with different PLL bandwidth with current feedback control.

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