Contact Us
RESEARCH

Single-Stage vs. Two-Stage for 12V VRM (2003)

The state-of-the-art VR design is based on the single stage multi-phase buck converter. The VR is operated at around 300KHz and the bandwidth is designed around 50KHz . To reduce the output capacitance, the switching frequency should be increased. However, the efficiency of today's single stage suffers at higher switching frequencies. The major loss factors are the switching losses and the body diode losses. If the input voltage of the multi-phase VR is operated as a low voltage, the VR efficiency can be improved. Inspired by this observation, CPES proposed a two-stage approach. (VTIP NO.04.042) The first stage can be designed at relatively low switching frequency to step down the input voltage from 12V to around 5V in the desktop application. With the lower input voltage, the switching loss of the second stage, which is proportional to the input voltage, is dramatically reduced. Therefore, compared with single stage approach, two-stage can achieve higher efficiency at even higher switching frequency. This two-stage design can eliminate the bulk capacitors while satisfying the transient response requirement. Therefore, the two-stage is more cost-effective compared with the single stage with a 30% total cost reduction, while achieving higher total efficiency.
INDUSTRY PARTNERS
CPES Intranet | Contact Us Copyright © 2017 Virginia Tech Center for Power Electronics Systems