Become a Member
Become a Member
RESEARCH
  2. Research
  3. Showcase
  4. 49

Proposed Power Architecture Change (2003)

Year: 2003
The inexorable increase in microprocessor clock frequencies and power requirements result in transient requirements far greater than today's technologies can effectively address. Incremental improvements simply will not provide the required regulation and control. To reduce the number and type of capacitors, a two-stage solution, where the first stage is a 5-7V conversion which could be a standard buck type of solution and the second stage operates at considerably higher frequency, say 4 MHz multi-phase voltage regulator module (VRM), has been demonstrated to dramatically reduce the number of bulk and cavity capacitors. By placing the 2nd stage on the Olga board or LGA board or very close proximity to the board, the interconnect impedance can be greatly reduced and as a result of that, it can result in significant reduction in the use of capacitors we are able to significantly reduce unwanted parasitic impedances.

Nowadays, Intel is investigating a two-stage solution and this stage shows a particular version of imitation of two-stage solution and placing the VR on the Olga board.

Return to CPES Showcase

Our Industry Partners

About CPES

Events/Presentations

Education

Interested in Becoming a CPES Member?

Learn more


Having technical issues?

Get Help

Copyright © 2021 Virginia Tech Center for Power Electronics Systems