A Novel Phase Lock Loop (PLL)-Based Interleaving Structure for Variable-Frequency Controlled Voltage Regulators
Ramp Pulse Modulation (RPM) has recently become widely used in the latest voltage regula-tor (VR) design of power microprocessors. The light load efficiency is as good as Constant On-Time (COT) control. Also, it saves more output capacitors than COT control, because both on time and off time can change immediately to improve load transient response. However, the switching frequency (fsw) varies due to input voltage (Vin) and output voltage (Vo) changes, which makes interleaving challenging. Currently, a pulse distribution structure has been pro-posed to achieve interleaving and minimize frequency variation. Nevertheless, three issues limit its performance: first is the inability to overlap PWM signals during transient; second is the noise sensitivity caused by the ripple cancellation effect of the summed inductor current feed-back; third is the reduction of fsw variation, which is not enough to minimize the impact on efficiency, and also generate a beat-frequency ripple by interacting with other VRs in a system.
This paper proposes an interleaving method incorporating PLL to solve all above issues. Fig 1(a) shows the dual-phase configuration, where two PLL forces D1 and D2 follow two fixed-frequency clocks (fCLK1, fCLK2) in 180° phase shift by slowly adjusting on time through on-time control signals (Von1, Von2). The benefits are as following: firstly, D1 and D2 can be naturally overlapped to speed up the load transient, as shown in Fig. 1(b); secondly, since Vc compares with the individual phase current, the current feedback does not suffer a ripple cancellation; thirdly, since the steady-state fsw is locked with fCLK, so VR can operate at an optimal efficiency point; fourthly, the beat frequency ripple current is eliminated by synchronizing the clock frequency of every VR controllers in a multi-processor motherboard.
The loop gain of the PLL loop (TP) in Fig. 1(a) is analyzed by a proposed small-signal model, and the compensation guideline is provided. Moreover, enlightened by the model, an adaptive PLL loop is presented to simplify the loop compensation by auto-tuning the control bandwidth anchored at the peak phase margin, as shown in Fig. 2. After that, a hybrid interleaving technique, a combining pulse distribution method, and a PLL method are developed to significantly reduce the circuit complexity by using the PLL loop for the high phase number application, all while transient performance remains comparable. Finally, the simulation and experimental re-sults verify the proposed method.