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Impact and Compensation of Dead Time on Common Mode Elimination Modulation for Neutral-Point-Clamped Three-Phase Inverters
Year: 2013
Fig. 1. Three level voltage source inverter system.
To overcome the penalty for adding DT, a compensation method can be applied based on the switching states analysis of each 3L phase leg. The impact of DT on CM voltage generation can be calculated as shown in Fig.2. To eliminate this impact, a compensation algorithm is proposed as shown in Table I.
System verification results show that the CM noise can be reduced significantly with this compensation method. Moreover, there is less distortion in the output current.
Fig. 2. Impact of DT on CM voltage generating in one swithcing period.
Figure 3. Dead time compensation algorithm.
Fig. 4. System test results; With0.5us DT: Green; with 1us DT: blue, with 1usDT and DTcompensation : pink.
