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A Wire-bond-less 10 kV SiC MOSFET Power Module with Reduced Common-mode Noise and Electric Field

Year: 2019 | Author: Christina Dimarino | Paper: T4.1
schematic
Fig.1. Schematic of the testing setup (a) without and (b) with the CM screen connected.
10 kV silicon carbide (SiC) MOSFETs can switch higher voltages faster and with lower losses than silicon devices while also being smaller in size. However, these features can result in premature dielectric breakdown, higher voltage overshoots, high-frequency current and voltage oscillations, and greater electromagnetic interference. In order to mitigate these side effects, and thus fully utilize the benefits of these unique devices, advanced module packaging is needed. This work proposes a power module package with a small footprint (68 mm × 83 mm), low gate- and power-loop inductances (4 nH), increased partial discharge inception voltage (53 %), and reduced common-mode (CM) current (ten times). The module uses molybdenum posts and direct bonded aluminum (DBA) substrate for the interconnections instead of wire bonds. This 3D structure reduces the parasitic inductances and capacitances, and allows decoupling capacitors to be integrated inside the module without increasing the footprint. To reduce the electric field strength at the ceramic-metal-encapsulant interface (i.e., the triple point) and the CM current generated by the fast voltage transients (up to 200 V/ns), it is proposed to stack two DBA substrates, and connect the middle metal to half of the dc bus (the midpoint of the series embedded decoupling capacitors in this case). With this connection, the partial discharge inception voltage (PDIV) is increased by 53%. This connection also forms a screen that contains the CM current within the power module. Fig. 1a and Fig. 1b show the schematics of the module double-pulse test without and with the middle metal layer of the substrate stack connected to the capacitor midpoint, respectively. CP1 and CP2 are the parasitic capacitances across the two DBA substrates. Fig. 2 shows the resulting experimental waveforms. The current flowing through the ground path (shown in Fig. 1) is reduced by ten times when the proposed screen is connected. This method is thus effective at both increasing the PDIV and reducing the CM current and does not add significant size or complexity to the power module. The lower CM noise can reduce the external filtering requirements and enable WBG devices to switch at faster switching speeds, thus reducing size, weight, cost, and losses at the system-level.
experimental waveforms
Fig. 2. Drain-source (red, left axis) and ground current (purple, right axis) waveforms with and without the CM screen.

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