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Bayesian Optimization of PCB-Integrated Field Grading for a High-Density 10 kV SiC Power Module Interface

power module cross-section
Fig.1. SiC 10 kV power module cross-section
  High-voltage SiC MOSFETs have the potential to drastically improve the size and efficiency of power systems due to their higher operating voltages and faster switching speeds. To realize this potential, a 10 kV/75 A high-density (4 W/mm2) SiC MOSFET package with low parasitic in-ductance (4.4 nH) was developed. The high-density design is enabled by minimal (6 mm) spacing between the terminals of the module. This is nearly six times closer than the terminals of the CREE XHV-9 10 kV SiC MOSFET module, which has a terminal spacing of 37 mm. The reduction in terminal spacing is made possible by fully enclosing the terminals, which circumvents the creepage and clearance distance requirements (Fig. 1).

  To reduce the electric field strength in the air surrounding the interface, copper traces inside the PCB are used as field-grading plates that shift the peak electric field from the air to the FR4 dielectric, which has a higher breakdown field strength than air. The geometry and location of the field-grading plates is critical to their effectiveness. To design the geometry, a numerical optimi-zation technique is used in conjunction with finite element analysis. The system is first decom-posed into critical 2D design regions, which are then parameterized, and the locations of field crowding are identified. A weighted cost function is formulated using the breakdown strength of the materials and is optimized using an interior-point algorithm with finite difference derivatives.

  One of these optimized cross-sections is shown in Fig. 2. The optimization results in copper conductors shaped such that the high strength electric field is contained inside the FR4 dielec-tric, where the field can be supported without partial discharge. Meanwhile, the electric field in air is kept below the breakdown strength of air, resulting in safe, reliable, partial-discharge-free op-eration. The optimized laminate bus bar and optimized module housing were built and experimen-tally demonstrated a partial discharge inception voltage of 11.6 kV rms under 60 Hz sinusoidal excitation.

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