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Active Gate Drivers for EMI and dv/dt Control

operation diagram
Fig. 1. Active gate driver turn-on waveform.
  This research presents a study on the impact of using active gate drivers which provide a variable drive voltage to the switching device. This will give a better understanding of the advantages and drawbacks seen with the introduction of multiple drive voltage variations. The primary areas of focus are on control of drain node dv/dt, switching loss and gate terminal current. One benefit seen from using an active driver includes control over drain node dv/dt such that with an active gate driver and lower gate resistance the same slew rate can be achieved as with a conventional driver and much higher gate resistance. This is simultaneously achieved with a lower switching loss in the active gate driver. Fig. 1 depicts both the conventional gate driver voltage profile in dashed red and an approach used by active gate drivers for dv/dt control. This also illustrates the two separate control regions available for the active gate driver to impact.

  When looking at reduction in dv/dt, simulations were performed using the C2M0080120D CREE SiC MOSFET. From these simulations the intermediate step voltage and duration of this voltage were adjusted. The results are plotted in Fig. 2 which shows the dv/dt being reduced from ∼ 110 V/ns to ∼ 30 V/ns (with an 8 V applied step). This represents a reduction of almost 73%. These results show a noticeable range in dv/dt reduction with an active driver. Through the introduction of additional intermediate voltage steps the results did not show any noticeable improvement in this area.

  From the perspective of loss Fig. 2 shows a clear trend as the step duration increases the losses also increase until a point where the dv/dt no longer is reduced, then loss remains constant.

  A final improvement noted in initial simulations is with the peak gate current during the drain voltage fall region. With the introduction of additional voltage steps in the gate driver voltage that achieved the same dv/dt, the peak gate current in this region was reduced and the current stayed at a more constant value.
simulation waveform
Fig. 2. Single Voltage Step Impact as Step Duration is Increased.

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