Average Modeling and Control for Three-Phase Three-Level Non-Regenerative Rectifier with Unbalanced DC Loads
The non-regenerative three-level boost rectifier, known as a Vienna-type rectifier, as shown in Fig. 1, is characterized by a reduced number of active switching devices, a high input power factor, and low device voltage stress, which make it a suitable topology for medium- and high-power applications with high power density. In addition, due to the three-level neutral point clamped (NPC) structure, the Vienna-type rectifier can feed two individual loads with partial and/or full dc-link voltage. Therefore the Vienna-rectifier potentially can reduce the cost and provide more design flexibility for the system architecture in the applications, such as telecommunication equipments, where the dc-bus structure with multiple voltage levels is considered.
However, an essential requirement of three-level NPC structure is to maintain the balance of the two dc-link capacitor voltages. Any unbalance can cause low frequency harmonics voltage on the ac side, and lead to higher voltage stress on the bridge devices and capacitors. For realization of feeding two individual load systems at the same time, the uneven power distribution to the two capacitor voltages could occur and therefore the voltage balance control is a challenge.
However, because of the asymmetric of paralleled VSCs in hardware or control, circulating current can be generated, which may increase the power loss, saturate the passive components and even damage healthy devices. The problem is even worse if interleaving and DPWM are used together, because of additional common mode (CM) circulating currents are introduced. Such CM circulating current has a frequency close to fundamental component and is the main reason why interleaving and DPWM are usually considered impossible to be used together in paralleled VSCs system.
This paper proposes a new average model and a control approach for the three-phase three-level non-regenerate rectifier (Vienna-type rectifier) with unbalanced dc load. State space analysis is first carried out to achieve the relationship between the voltage unbalance, load conditions and the control duty cycle. With the implementation of an optimum zero-sequence component, a simplified average model for the dc output stage with unbalanced load is obtained. Based on the developed model, a new control approach and the criteria of control parameter selection are presented. The simulation and experiment results shown in Fig. 2 validate the proposed control scheme.