Phase-Locked Loop Noise Reduction via Phase Detector Implementation for Single-Phase Systems
A crucial component of grid-connected converters is the phase-locked loop (PLL) control subsystem that tracks the grid voltage's frequency and phase angle, as shown in Fig. 1. Therefore, accurate, fast-responding PLLs are required to provide these measurements for control and protection purposes. Illustrated in Fig. 2, this paper proposes a novel feedback mechanism for single-phase PLL phase detectors (PDs) using the estimated phase angle. Ripple noise in the estimated frequency, most commonly a 2nd harmonic under phase-lock conditions, is reduced or eliminated without the use of low-pass filters (LPFs), which can cause delays to occur and limit the overall performance of the PLL response to dynamic changes in the system.
The proposed method has the capability to eliminate the noise ripple entirely, and under extreme line distortion conditions can reduce the ripple by at least half. Other modifications implemented through frequency feedback are shown to reduce the settling time of the PLL up to 50%. The noise reduction can be easily seen in Figs. 3 and 4, which show the transient response of the proposed PLL system and the typical mixer-type PLL system. Mathematical analyses with simulated and experimental results are provided to confirm the validity of the proposed methods.