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A Droop Controller is intrinsically a Phase-Locked Loop

Year: 2013
Fig. 1. Enhanced phase-locked loop (EPLL).
In order to address the energy and sustainability issues being faced worldwide nowadays, more and more renewable energy sources are being connected to power systems, often via DC/AC converters (also called inverters). These inverters are required to synchronize with a connected system. Another important requirement for these inverters is that they should take part in the regulation of system frequency and voltage, in particular, when the penetration of renewable energy exceeds a certain level.

There are many ways to synchronise an inverter with the grid but the most commonly adopted strategies are based on phase-locked loops. A basic phase-locked loop (PLL) adopts a control loop to track the phase of an input signal. It can often provide the frequency information of the signal as well, but normally without the information of the voltage amplitude. Also, in order to obtain the amplitude information of the input signal, the enhanced PLL (EPLL) shown in Fig. 1 can be adopted.

What is fundamental to the operation and regulation of the frequency and voltage of a power system is the so-called droop control strategy. It was originally adopted to operate synchronous generators and has recently been adopted to operate inverters connected in parallel. The generators and/or inverters change the reactive power and real power output according to the system voltage and frequency. The conventional droop control strategy is often regarded as a static control law. It actually includes an integral effect in each channel. After some manipulations, the droop controller can be drawn in an equivalent form shown in Fig. 2 (for the case with resistive impedance). The filter H(s) is a hold filter so it does not cause any major difference.

Comparing these two figures, it can be seen that they are more or less the same. In other words, a droop controller is intrinsically an (enhanced) phase-locked loop. Both figures have two channels: a frequency channel and a voltage channel. When the voltage channels are ignored, what is left in Fig.2 is the frequency droop control and what is left in Fig. 1 is a basic PLL. This means the frequency droop control is intrinsically a basic phase-locked loop.

What is discovered in this study opens up several lines for future research: (1) PLLs can be improved by adopting what is done to droop control strategies; (2) Droop control strategies can be improved via looking at the vast literature of PLLs; (3) It is a challenge to analyze the stability of systems with more than one droop controller. What is done in the PLL community about the stability of PLLs can be borrowed; (4) A dynamic droop controller can be designed to improve the performance of droop control.

Fig. 2. Droop control for systems with resistive impedance.

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