Impact and Compensation of Dead Time on Common Mode Elimination Modulation for Neutral-Point-Clamped Three-Phase Inverters
The voltage-source pulse-width modulation (PWM) inverter has made a significant contribution to achieving energy conservation as well as improving system performance and productivity in many applications such as variable frequency motor drives, uninterruptible power systems and renewable energy systems. Compared with two level voltage source inverters, neutral-point-clamped (NPC) inverters can achieve better performances on ripples, harmonics and EMI. The common mode elimination (CME) modulation is a well-known modulation method which can theoretically eliminate the common mode voltage, however, in the real implementation, due to the existence of dead time (DT) to avoid shoot through problem during operation, the real benefit from CME modulation is limited and the penalty on voltage utilization ratio and the loss of neutral voltage balancing capability make this modulation method less practical.
To overcome the penalty for adding DT, a compensation method can be applied based on the switching states analysis of each 3L phase leg. The impact of DT on CM voltage generation can be calculated as shown in Fig.2. To eliminate this impact, a compensation algorithm is proposed as shown in Table I.
System verification results show that the CM noise can be reduced significantly with this compensation method. Moreover, there is less distortion in the output current.