A Frequency-Domain Study on the Effect of DC-Link Decoupling Capacitors
DC-link decoupling capacitors are generally placed near the power switches in the converter to minimize the parasitic ringing and voltage overshoot on the devices. We have studied the influence of decoupling capacitors on the turn-off parasitic ringing of power MOSFETs in the frequency domain based on a small-signal modeling approach. This new angle helps explain the effect of these capacitors in a simpler and more straightforward way than the traditional time-domain analysis, and provides a deeper insight into the problem. A rule of thumb about the selection of effective decoupling capacitance value can also be derived from this study.
Fig. 1 shows the small-signal model with the decoupling capacitance. It is assumed that LDS represents the minimum possible stray inductance associated with the device packages and the shortest necessary interconnections to access the decoupling capacitance CDec. The interconnection between the voltage source and the power stage, such as the DC bus bar, will then introduce an additional stray inductance L1. Generally, CDec needs to be placed as near as possible to the power stage to minimize LDS, and 50 to 100 times COSS is a sufficient value for CDec to achieve the decoupling effect. Further increasing CDec will not help improve the ringing caused by LDS and COSS, which is determined by the packaging technology (e.g. the parasitics inside a power module) and the device characteristics. When fully decoupled, L1 will not affect the high-frequency ringing, but will generate another resonant peak with CDec located at 1/(L1CDec) and cause low-frequency oscillation.
Fig. 2(a) shows the double-pulse circuit used to study the effects of parasitics. Fig. 2(b) shows the impedance measurement results at four discrete values of CDec, which is consistent with the turn-off waveforms of the MOSFET.