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Avoiding Si MOSFET Avalanche in Cascode Device and Achieving Zero-Voltage-Switching for Cascode Device

Year: 2014
Fig. 1. Cascode structure for normally-on devices.
High-performance active devices have consistently proven to be the first force to increase power density and meet the requirement of modern systems. Silicon (Si) devices have dominated power management since the late 1950s. However, after several decades of optimization and development in the production process, the Si device has approached its theoretical limits, and material properties have become the limiting factor. Based on the rapid development of research in recent years, high-voltage normally-on wide-band-gap devices have been proven to have better performance compared to the Si MOSFET. With high electron mobility, high breakdown voltage, low on-resistance, low input capacitance, and high thermal conductivity, the wide-band-gap device is more suitable for high-frequency, high-efficiency, and high-power-density applications.

The cascode structure shown in Fig. 1 is used to make the terminal a normally-off device. The Si MOSFET controls the on/off state of high-voltage normally-on devices. The interaction and parasitic capacitance of the two devices plays an important role in achieving high efficiency, especially under soft-switching conditions. The two devices should be well matched. Otherwise, the Si MOSFET may have an avalanche breakdown during the turn-off process. Although the avalanche voltage of Si protects the high-voltage normally-on device from the damage of over-voltage, avalanche is not recommended operation for the Si MOSFET, and it is a potential risk to the reliability of the device. The energy dissipated through the avalanche path brings additional loss. Moreover, the avalanche of an Si MOSFET will break the charge balance of the parasitic capacitors of the MOSFET and the high-voltage normally-on device, which will cause the device to lose its zero-voltage turn-on condition internally during the soft-switching turn-on process. This is undesirable, especially in applications that operates at MHz frequency.

After analyzing the voltage distribution process of the cascode device in detail, and quantifying the conditions under which Si will reach avalanche and the avalanche loss, we have devised a simple and effective solution which is paralleling an external capacitor with drain-source of Si MOSFET to compensate the junction capacitors charge mismatch and thus avoid Si reaching avalanche. This solution also achieves zero-voltage-switching for high-voltage, normally-on devices.

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