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Evaluation of GaN-Based MHz Interleaved CRM PFC Converter

Fig. 1. (a) Adaptive PLL loop: Block diagram.
Constant on-time control is widely used for better light-load efficiency, and faster transient response to save output capacitors. However, its nature of variable frequency control causes wide variation in switching frequency (fsw) under input voltage (Vin) and/or output voltage (Vo) changes, which makes interleaving difficult. Phase manager and Phase Lock Loop (PLL) are two common solutions. The former is simpler, but is noise-sensitive by ripple cancellation effect and is unable to synchronize PWM signals among phases during transient. The latter is less noise-sensitive and allows overlapping PWM signals, but requires a PLL loop per phase. Also, the PLL loop has a stability issue, when the bandwidth (Tp) is designed too high or too low.

This paper first provides an accurate small-signal model to understand the dynamics of the PLL loop, and gives design guidelines for the Low Pass Filter (LPF) of PLL to avoid the stability problem. Then, an adaptive PLL loop is proposed to maintain a constant Tp bandwidth over a wide duty cycle range. Thus, the PLL loop design becomes simple and has fast tracking to fclk without interfering with constant on-time control loop. As shown in Fig. 1, a proposed adaptive PLL loop maintains a constant gain by using Vin and Vo feedforward at on-time generator, and Vo feedforward at Phase Frequency Detector (PFD) of PLL. Secondly, a novel hybrid interleaving structure is developed with a comparable noise immunity and transient response as the PLL method, while the number of PLL loops is greatly reduced. For a 4-phase operation as shown in Fig. 2, it contains two phase managers that maintain a 180° phase difference for each of the two phases, and only one PLL locks 90° difference between D1 and D3. 3 PLL loops are saved when compared with the PLL method. Fig. 3 shows PWM overlapping during transient naturally. Finally, the simulation result based on the state-of-art filter model of the laptop VR demonstrates the constant output impedance design for an AVP over a wide duty cycle range.


Fig. 1. (b) Simulated Tp Loop gain.
Fig. 2. (a) 4-phase hybrid interleaving: Block diagram.



Fig. 2. (b) Transient response.
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