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Model-Based Design of a Modular Multilevel Converter with Minimized Design Margins
Fig. 1. Circuit configuration of a modular multilevel con-verter
In this paper, a new approach is proposed in which different sources of uncertainties that cause the mismatch between modeling and simulation predictions and real system behavior are identified and characterized so that they can be predicted ahead of time to eliminate the use of large safety margins (shown in Fig. 2). Using this approach, modeling and simulation results can be used during the early design stages with confidence in their predictive proficiency and accuracy.
In the first section, an overview of the verification, validation, and uncertainty quantification (VV&UQ) process is described as enabling us to identify, characterize and quantify different sources of uncertainties in modeling, simulation, and experiment. In the second section, the concept from the first section is employed to calculate and minimize the required design mar-gins by using probabilistic modeling and simulation. To this end, the peak voltage across the semiconductor device in an MMC (shown in Fig. 1) - which is a key variable used to size the capacitor bank - is selected as an example to illustrate the methodology proposed in this paper.
Fig. 2. Final probability box of maximum voltage across semiconductor device indicating total uncertainty
