High-Efficiency Two-Stage 48v VRM with PCB Winding Matrix Transformer
High efficiency power supply solutions for data centers are gaining more attention in order to minimize the fast growing power demands on these loads. The 48v VRM, which is used for powering CPU, is a promising solution replacing the legacy 12v VRM in order to minimize the bus distribution loss, cost and size. In this paper, a two stage solution for 48/1.8v-120A VRM is proposed. The first stage is a LLC converter operating as a DC/DC transformer (DCX) that provides an isolated unregulated bus voltage (12v). This voltage is stepped down by a multiphase buck converter in order to supply the CPU with the desired voltage.
The concept of the Matrix transformer was used to design the first stage high frequency transformer. An enhanced termination was proposed by embedding the secondary synchronous rectifiers (SRs) as shown in Fig.1 resulting in a significant reduction in both leakage inductance and winding AC resistance. Fig.2 (a) shows the field intensity plot where there is no higher field intensity at the termination part, while Fig.2 (b) shows that there is no higher current crowding at the termination part of the transformer showing the benefit of SR integration in the winding. The designed 250W converter achieved a power density of 870 W/in3 and a peak efficiency of 97.3% as shown in Fig.3.
This paper proposes to change the primary side of the DCX from a full-bridge structure to a half-bridge structure in the light load condition dynamically, so that the output of LLC DCX can be changed from 12V to 6V. This increases the overall light load efficiency significantly due to the reduction in core loss of the LLC DCX and the reduced switching loss of multi-phase VR. Combining this with phase shedding during light load will result in significant light load efficiency improvement.
The two stage solution was experimentally tested resulting in a peak efficiency of 91%. The light load efficiency with the proposed method showed an 8 point increase over the fixed bus voltage as shown in Fig.4.