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Thermal Analysis and Improvement of Cascode GaN Device Package for Totem-Pole Bridgeless PFC Rectifier

Fig. 1 The cross-sectional temperature distribution of the built thermal model for the stack-die packaged cascode GaN device (Power loss = 8.8 W, Ta = 25 °C).
The totem-pole bridgeless power factor correction (PFC) rectifier has a simpler topology and higher efficiency than other boost-type bridgeless PFC rectifiers. Its promising performance is enabled by using high-voltage gallium nitride (GaN) high-electron-mobility transistors, which have considerably better figures of merit (e.g., lower reverse recovery charges and less switching losses) than the state-of-the-art silicon metal-oxide-semiconductor field-effect transistors. Cascode GaN devices in traditional packages, i.e., the TO-220 and power quad flat no-lead, are used in the totem-pole PFC boost rectifier but the parasitic inductances induced by the traditional packages not only significantly deteriorate the switching characteristics of the discrete GaN device but also adversely affect the performance of the built PFC rectifier. A new stack-die packaging structure with an embedded capacitor has been introduced and proven to be efficient in reducing parasitic ringing at the turn-off transition and achieving true zero-voltage-switching turn-on. However, the thermal dissipation capability of the device packaged in this configuration becomes a limitation on further pushing the operating frequency and the output current level for high-efficiency power conversion. This paper focuses on the thermal analysis of the cascode GaN devices in different packages and the GaN-based multichip module used in a two-phase totem-pole bridgeless PFC boost rectifier. A series of thermal models are built based on the actual structures and materials of the packaged devices to evaluate their thermal performance. Finite element analysis (FEA) simulation results of the cascode GaN device in a flip-chip format demonstrate the possibility of increasing the device switching speed while maintaining the peak temperature of the device below 125 °C. Thermal analysis of the GaN-based power module in a very similar structure is also conducted using the FEA method. Experimental data measured using the fabricated devices and modules validate the simulation results. The developed new package in a flip-chip configuration enhances the thermal dissipation capability of the cascode GaN device in the stack-die format. The GaN-based power module built using the same packaging structure also demonstrates desirable thermal performance.

Fig.2 Thermal analysis for the GaN-based power module (Total power loss = 34 W, Ta = 20 °C)
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