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Ultra-Low Inductance Vertical Phase Leg Design with EMI Noise Propagation Control for Enhancement Mode GaN Transistors

Year: 2016
Fig. 1. (a) Gate driver circuit design
In order to extract the full benefits from the enhanced-mode lateral GaN devices, this paper presents an improved phase leg power loop design with a CM noise current propagation control for a 650V/30A enhancement mode GaN switch (GS66508) from GaN systems. Based on the static characterization results, a gate drive circuit design is presented considering the CM noise current propagation control. By controlling the propagation path impedance of the digital control circuits and their power supply circuits to control more conductive CM noise propagate through power supply path to protect the digital control circuits. The design is verified through experiments on a phase leg prototype which proves the effectiveness of the proposed phase leg on the overvoltage reduction during current transition. It also verifies that less cross-coupling between power loop and gate loop is needed when compared with a conventional lateral power loop design. Finally, a full bridge voltage source inverter is designed and tested based on the proposed phase leg using a time domain and frequency domain measurement that verifies the effectiveness of the CM noise propagation control.

The high switching speed of GaN devices will generate a high dv/dt that can induce high CM current that propagates from power loop to gate loop. The main propagation path is through the stray capacitance of the isolated power supplies and digital isolators as shown in Figure 3. In order to improve the electromagnetic compatibility of the system, CM noise propagation is controlled by differentiating the propagation path impedance of the digital control circuits and their power supply circuits. The block diagram is shown in Figure 1, where digital isolators with ultra-low isolation capacitance are selected for both top and bottom devices to provide good isolation for high frequency EMI noise. The power supply of the digital control circuit is also selected with an ultra-low isolation capacitance to create a high impedance path to reduce CM noise current through the digital control circuits. Meanwhile the gate driver power supply is selected with a relatively higher isolation capacitance to create a lower impedance path for CM noise. In addition, CM chokes are added to both the signal and power supply path to maintain a higher impedance at high frequency. The selection of the choke impedance also needs to ensure that the digital control circuits have a higher noise propagation path impedance than its power supply. In this configuration, the digital control circuit will have an ultra-high propagation path impedance and the gate drive power supply will provide a bypassing path with a relatively low propagation path impedance in parallel with the digital control circuits which can effectively reduce CM noise current through the digital control circuits. With the proposed design, gate drive power supply circuits will sustain the high CM current, however, the power supply control circuits should have higher susceptibility and noise immunity considering its relatively smaller dimension and higher circuit integration level.

Fig. 1. (b) Gate driver circuit design with CM noise propagation control

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