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Gate Driver with Overshoot Regulation and Active Snubbing
Fig.1. Proposed ORAS and its functional blocks. Peak detector senses vds into vdsmax. vdsm is the sampled output of voltage divider and sample-and-hold from vdsmax. Vref and vdsm are compared in a PI-controller. Controller output vc decides the time delay from vhgs to vhgTD. A delay self-clamping signal vg_QL drives QL and changes vgsmin. vgsmin alters vdsmax.
We developed an overshoot regulator on the gate driver to control vds stress on the device during low-side turn-off. Compared with existing methods, the ORAS only needs negligible energy to clamp overshoot. Peak voltage vdsmax can be regulated with a closed-loop feedback by controlling the timing of Self-Clamping.
The proposed regulator is simulated on a synchronous buck converter, which is proven to be stable for different values of Vdsmax, loads and line transients. By increasing the snubber, maximum vds is reduced from the original 29 V to 20 V by ORAS and 1/6 of the loss is achieved by increasing gate resistance. Furthermore, the EMI level is 12dB lower in the FM frequency band by using ORAS.
Fig. 2. Top: Vds and Vgs waveforms under 20 V, 25 V regulation, and no overshoot regulation. Bottom: Vdsmax = 19.8 V, 25.1 V, 28.8 V in 20 V, 25 V, and no regulation.
Fig. 3. Fig. 3. Power losses in different voltage reduction methods. When Vdsmax is 20 V, the loss in the ORAS is reduced to 1/2 the loss by using the RC snubber, and 1/6 loss by increasing Rg.
