Ultra-Low Inductance Phase Leg Design for GaN-Based Three-Phase Motor Drive Systems
In order to extract the full benefits from enhanced-mode lateral GaN devices, this paper presents an improved phase leg power loop design with vertical power loop structure and CM noise current propagation control for a 650V/30A enhancement mode GaN switch (GS66508) from GaN systems. The static characterization results are presented to verify the better performance of the GaN switches as compared to the Si MOSFETs. Based on the static characterization results, a gate drive circuit design is presented. It takes CM noise current propagation control into consideration the by controlling the propagation path impedance of the digital control circuits and their power supply circuits in order to control more conductive CM noise propagate through power supply path to protect the digital control circuits. Moreover, a vertical power loop layout is proposed to minimize the current commutation loop inductance. The design is verified through experiments on a phase leg prototype which prove the effectiveness of the proposed phase leg on the overvoltage reduction during current transition. It also verifies that there is less cross-coupling between the power loop and gate loop when compared with conventional lateral power loop design. Finally, a three phase motor drive system is designed and tested based on the proposed phase leg.
A vertical power loop design is proposed and shown in Figure 1. GaN devices are mounted on both sides of the PCB board and figure 1 shows the current loop and gate loop in the proposed design, where the power loop is folded to increase the mutual coupling between the current through the two devices and the decoupling capacitor is mounted near the devices as close as possible, therefore the current commutation loop inductance can be reduced significantly compared with the reference design, For lateral GaN devices, the current conducts along the devices, therefore the proposed vertical layout is more suitable for lateral devices compared with vertical devices. The parasitic loop inductance estimation through Q3D extraction shows that the power loop inductance is reduced 10 times as compared with the reference lateral power loop layout design. Figure 1(b) also indicates that the gate loop is perpendicular to the current loop which can also reduce the near field coupling due to the high di/dt in the current commutation loop. Moreover, the DC input and AC output terminals are separated in the proposed layout, which reduces the interaction between input and output noise. The thermal design is more challenging in the proposed layout since the devices are overlapping each other and the heat has to dissipate along the PCB board. The heat dissipation can be improved by implementing the power loop with direct bonded copper (DBC) or by using the newly-released top-cooled devices.