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Large Substrates Bonded by Silver Sintering and Their Thermal Performance

Figure explaning silver sintering and assembly of substate and silver paste
Fig. 1. Large area bonding by silver sintering at low temperature.
Heat dissipation is a critical function of packaging power devices or modules. In a power package, heat generated by the device has to be conducted away through multiple layers of materials and bonded interfaces. One of the most important bonded interfaces is the thermal interface between the substrate and the heat spreader or heat-sink plate. The emerging sintered silver technology has been shown to offer significantly higher thermal and electrical conduction and higher reliability than the conventional soldering technologies for die-attachment, which is a promising alternative for large area bonding. The purpose of this study is to develop the large area bonding technique with silver sintering and then characterize the thermal properties. The DBA substrates were bonded together by silver paste under the heating profile shown in Fig. 1. To characterize bonding quality, thermal resistance was measured. A typical value for silver sintering is about 5 mm2k/W.

Silicon IGBT chips are mounted on the substrate. The IGBTs are used as a heat source as well as a temperature sensor. Transient thermal impedance or Zth measurement is performed by taking the ratio of junction temperature raise over the heating power. The package is modeled by a Foster network of capacitors and resistors, which corresponds to heat capacities and resistances of the materials or interfaces, respectively. Then, using electrical network theories and mathematical algorithms, the measured junction temperature response is transformed into a cumulative structure function of the package. The function represents a relationship between the cumulative thermal capacitance and cumulative thermal resistance from the device junction through the package. Finally the thermal resistance of the substrate attach layer is derived. By mounting multiple chips at different locations, the 2-dimension map of thermal resistance is plotted as shown in Fig. 2. The average value is 5.20, which is nearly the lowest amongst the thermal interface materials. The variation is 6%, which illustrates the bonding quality is uniform across the whole area.

Image of thermal resistance for bonding layer
Fig. 2. 2-dimension map of thermal resistance for bonding layer
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