Contact Us

Design of a Zero-voltage-switching Class E Inverter with Fixed Gain

Class-E Inverter
Fig. 1. Topology of a Class-E Inverter
It is difficult for Class-E inverters to maintain fixed gain or Zero-Voltage-Switching (ZVS) over a wide load range. A design methodology of a fixed-gain Class-E inverter is presented herein without adding components or using closed-loop controls. Zero-Voltage-Derivative-Switching (ZVDS) turn-on under nominal load condition, and ZVS turn-on under light load condition are achieved. Three times the power-output capability is obtained compared to the ZVS Class-E in-verter works only with a low level load since the parameters are designed for ZVS at no-load condition. The expectations were validated by a Class-E inverter switched at 6.78 MHz with 10-V input voltage and 25-W output power over 10:1 output power range. The topology of a Class-E inverter is shown in Fig. 1. The performance of the three designs are compared in Fig. 2 to summarize the contribution of this work. The traditional design offers ZVDS and ZVS under optimum conditions, but non-ZVS occurs with load variation. Some papers propose that ZVS and the output voltage be kept under light load, but the cost is high current stress and small power-output capability. The design method-ology in this work keeps ZVDS and ZVS under nominal load conditions and realizes ZVS and regulation at low-load condition with reduced current stress. Three times the power-output capability is obtained, compared to low-load ZVS design. In the complete paper, the operating principle of the ZVS Class-E with fixed gain is intro-duced. The detailed design steps are listed with the experimental verification of a 6.78 MHz inverter with 10 V input voltage and 25 W output power.
Fig. 2. Waveforms under (a) nominal load and (b) 10 % load condition of three designs of Class-E inverter.
CPES Intranet | CPES Forms | Conference Uploads | Contact Us Copyright © 2020 Virginia Tech Center for Power Electronics Systems