Become a Member
Become a Member


Distributed Control and Communication System for SiC-based Modular Impedance Measurement Unit

Year: 2019 | Author: Yu Rong | Paper: P3.2
System configuration
Fig. 1. System configuration of the PIU
The master-slave communication mode with bidirectional line topology is utilized in the distributed communication system of the perturbation injection unit (PIU), shown in Fig. 1. There are three main steps to run the system. The first step is the start-up address distribution to arrange the address number for each slave. The second step is the start-up synchronization to synchronize all of the slaves with the master. The third step is normal communication. During every cycle time, slaves send voltage and current to the master and generate gate signals, based on the calculated pulse width modulation (PWM) references received from the master. Some non-periodic information, such as the synchronization command, temperature, and fault signal, should also be transmitted during the normal communication step. For the synchronization of the communication system, the oversampling method is used in the clock and data recovery block to make the offset between nodes constant. The synchronization based on the precision time protocol (PTP), compensates the offset. An experiment is done with four field-programmable gate array (FPGA) boards, Altera MAX 10 10M08SAE144C8G; one is the master, and the other three are slaves. This experiment verifies the synchronization and communication protocol design. The square wave based on the local time counter of each node is observed. In the communication network, the clock frequency of the FPGA controller is 200 MHz, and the data rate is 40 Mbps. The synchronization among four nodes is realized. Zooming in, the maximum jitter of three slaves is 25 ns, as shown in Fig. 2. In summary, a distributed control and communication protocol has been designed and veri-fied for a power electronics building block (PEBB)-based PIU, and a new synchronization meth-od is implemented in the system. Compared with commercial chips, the forward delay per node can be reduced, and a communication frequency of 120 kHz is realized. The synchronization accuracy can be well controlled with the maximum jitter of 25 ns among four nodes.
Fig. 2. Synchronization among four nodes

Our Industry Partners