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Single-pulse, Common-mode-voltage, Pulse-width-modulation Scheme to Achieve High Power Density for Full-silicon-carbide, Three-level Uninterruptible Power Supply

Circuit diagram and equivalent model
Fig. 1.(a) Ac-ac stage circuit diagram of full-SiC three-level UPS. (b) Common-mode equivalent model.
Superior loss characteristics of wide-bandgap (WBG) devices are improving both the power density and efficiency of power electronics. As shown in Fig. 1, uninterruptible power supplies (UPSs), are one of the applications that may highly benefit from the low-loss characteristic of silicon carbide (SiC) MOSFETs. A double conversion efficiency can be as high as 98 %, while the power density of the power electronics system can be significantly improved, compared to silicon (Si)-based UPSs. An increase in switching frequency brings a change in the contributions of power electronics components on total volume. Firstly, the portion of electromagnetic interference (EMI) filters in the total volume increases, especially the common-mode (CM) part. Secondly, the contribution of dc-link capacitors may increase in three-level topologies, since the size of these capacitors is not relevant to the switching frequency. In this paper, a pulse-width modulation (PWM) scheme for three-level full-SiC UPSs was de-veloped to achieve a high power-density. Two key passive components were selected for size reduction of the full-SiC UPS: a CM EMI filter and dc-link capacitors. To reduce the CM noise and perform neutral point voltage balancing, an LMZ, MMS1, and MMS2 vector combination were proposed, based on a synchronous switching of three-phases. This is shown in Fig. 2. The proposed combinations align CM voltage (CMV) to be a single pulse per a switching period. In this way, CMV cancellation between a three-level rectifier and inverter in the CM equivalent circuit, shown in Fig. 1 (b), can be maximally utilized, while a drift of neutral point voltage can be pre-vented by a transition among three combinations. Secondly, to reduce the dc-link capacitors, a simple algorithm to compensate neutral point voltage fluctuation was proposed. When the small film capacitors are used for the dc-link, the fluctuation of NPV creates a low-frequency distortion on the output current. As the design of filter inductors seeks to be small, utilizing the benefits of both high switching frequency multi-level voltage, amount of the distortion can be more severe in a case of full-SiC multi-level inverters, compared to Si-IGBT based ones. Such a distortion can be easily compensated by modifying the carrier slope. Synchronous switching to reduce CMV can be maintained by a correction on the zero-sequence voltage. The proposed PWM scheme was verified with a 20 kW full-SiC UPS.
Description of modulation implementation
Fig. 2. Carrier-based implementation for LMZ and MMS vector combinations.
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