Design of a Multilayer Planar Bus for Medium-voltage dc Converters
ilicon carbide (SiC) allows wide-bandgap (WBG) devices to operate at higher voltages and switching frequencies. The adoption of these WBG devices means medium-voltage power elec-tronic converters can now advance rapidly. To fully leverage these SiC attributes, power loop inductance must be minimized. The DC-link bus is an area of opportunity for improvement. Re-ducing conductor spacing not only provides a smaller parasitic inductance, it can also decrease the converters overall size and weight; however, higher voltage actually requires an increase in conductor spacing. The manufacturing process for a traditional laminated bus increases the like-lihood for defects in high electric fields (E-fields) These defects coupled with a high field inten-sity increase partial discharge (PD) within the insulator. PD can cause premature system failure due to insulation degradation. This leaves designers with the tradeoff of increasing the bus thickness for reliability,or decreasing the thickness for improved switching performance. In this work, a low-inductance printed circuit board- (PCB-) based bus is designed to support Wolfspeeds XHV series 10 kV SiC MOSFET module. The construction process of a PCB exac-erbates challenges seen in a traditional laminated bus. A custom dielectric has been selected for PCB construction to further reduce the likelihood of voids; thus, further reducing the likelihood of partial PD. The E-field was analyzed in high-intensity regions using COMSOL for finite-element analysis (FEA). A midpoint layer separating the +/-DC layers was implemented to reduce the peak intensi-ty near the insulator/connector interface. Geometric techniques for field control along the surface and within the PCB were implemented using the design flow shown in Fig. 1. The results for the final E-field intensity after completion of the design flow are shown in Fig. 2. It should be noted that the field in air is of interest in the bottom image shown in Fig. 2; therefore, data above 2 kV/mm has been restricted and appears white. Simulation results show that the peak E-field intensity can be reduced by adding a slight offset between conductors at different potentials. Due to the voltages of interest, the E-field intensity in air was most efficiently controlled by forcing the field into an additional dielectric lay-er placed on the outside of what would normally be the outermost power plane. A prototype is being constructed for hardware validation.