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Optimization of Modular Filter for Multichannel, Three-phase Interleaved ac-dc Converters

Benchmark filter topology
Fig.1. N interleaved modular benchmark filter topology with CM choke for circulating current control
A cascaded LCLC filter stage is used as a benchmark topology to attenuate high-frequency electromagnetic interference (EMI) levels in order to satisfy the IEEE 61000-3-12, to meet total harmonic distortion (THD) specifications as per IEEE 519, and to regulate the individual current harmonic levels as per IEEE 1594. This filter stage utilizes circulating current introduced by symmetrical phase-shifted pulse-width modulation (PWM) control. The proposed filter can work as a standalone, parallel or interleaved configuration. Several constraints, such as limits on resonant frequency, reactive power, peak circulating current and thermal limits (&Delta TRISE) on inductor design are considered in the filter design process. Three converters are used as a test case, as shown in Fig. 1. The optimization algorithm is summarized in Fig. 2. Semiconductor loss includes conduction and switching losses while inductor loss includes dc+ac winding losses (skin, proximity effect) and core loss (iGSE ). An amorphous and nano-crystalline core library is selected for differential-mode (DM) and common-mode (CM) filter components, respectively, due to their high attenuation characteristics, low permeability variation with temperature, and high flux density limits. For simplicity, the same terminal model is used for the two- and three-level converter (NPC) for comparison purposes. The benefit of having three levels is observed at higher switching frequencies, and could result in lower filter volume; however, the overall filter volume requirement for EMI increases at such high frequencies. It was found that the peak circulating current decreases with higher switching frequencies; however filter loss increases as well, resulting in another design trade-off. Such trade-off issues are tackled using the optimization approach. The final design has been verified with simulation studies to meet EMI PQ and circulating current limit criteria.
Optimization algorithm
Fig. 2. BLLP based optimization algorithm
Comparison results
Fig. 3. Comparison between converter topologies and loss, Loss breakdown, circulating current check