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20 MHz, Three-via Two-phase Inverse Coupled Inductor Design for Integrated Voltage Regulator for Smartphone Applications

Magnetic integration
Fig.1. Three-dimensional magnetic integration for mobile application
For the magnetic integration in integrated voltage regulator (IVR), the on-chip inductor for wafer level integration and the package-embedded integration are two mainstreams. The on-chip inductor achieves ultra-high inductance density and small inductor size with a multi-turn structure. However, large dc resistance (DCR) limits current handling ability to < 1 A load current per phase. In mobile applications, the peak current demand for system-on-chip (SoC) load is 20 A or more. Increasing the phase number to supply enough power increases cost and control complexity. To solve this issue, package-embedded inductor integration with a larger current handling ability is selected. At the same time, in order to support dynamic voltage and frequency scaling (DVFS) and further shorten the power delivery path, a three-dimensional integration structure is proposed by CPES and shown in Fig.1, where an inductor is put underneath the processors rather than on the motherboard. To realize this, a unique inductor structure with a small footprint and low profile is required. In this paper, a unique, 20 MHz three-via two-phase inverse coupled inductor structure is proposed, as shown in Fig. 2. This special structure combines the benefits of multi-via with boosted inductance density and inverse coupling with dc flux cancellation effect. First, different high frequency magnetic materials are compared with our high frequency magnetic material characterization method. Metal-flake composite manufactured by TOKIN Corporation is selected for its high permeability and low loss property. Then, the impact of the design parameters of this structure is carefully examined and the whole inductor design flow is proposed for optimization with the help of ANSYS Maxwell simulation software. Finally, the inductance and coupling are measured by hardware to verify the accuracy of the simulation models. The final results show the total loss of inductor is as small as 100 mW at 3 A load current with a 2 mm2 footprint and 0.5 mm height per phase. Compared with our previous single-via five-phase inductor design, this new three-via two-phase inverse coupled inductor achieves a 50 % loss reduction and 30 % size reduction. The comparison results with state-of-art inductor designs for IVR for mobile applications also indicates this new structure is promising due to larger current handling capability and smaller size. To develop a 20-50 MHz IVR for smartphone applications, this paper proposes a 20 MHz, three-via two-phase inverse coupled inductor structure. The design flow is developed for optimization and experiments verify the accuracy of the simulation model. Compared with state-of-art inductor design for mobile applications, this new structure has larger current handling capability, a smaller footprint, and low loss and profile.
3D view of inductor structure
Fig.2a. 3D view of three-via two-phase inverse coupled inductor structure
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2D view of inductor structure
Fig.2b. 2D view of three-via two-phase inverse coupled inductor structure
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