Commutation Loop Analysis and Optimization for a SiC- Based 25 kW, 380:460 V Three-Phase Matrix Converter
Reduction of commutation loop parasitics is crucial for the operation of wide bandgap devices. Higher di/dt, and dv/dt rates during switching transients of SiC MOSEFTS cause greater overvoltages and ringing from stray inductances. Decreasing parasitics is especially important for a three-phase matrix converter application, which has 3 phase legs and 9 power loops, as shown in Fig. 1. 3D printed circuit board (PCB) layout strategies can be applied to design symmetrical, lower inductance commutation loops.
Overlapping power traces cause magnetic flux cancellation, which in turn reduces overall loop inductance. This gain is limited by the presence of parasitic capacitances induced by the interaction of jumping nodes. Trade-offs between these factors must be considered when designing the layout of the PCB. Thermal management must also be assessed in the layout of the commutation loops, as certain strategies inform constraints on the design. In this paper, various cooling methods are discussed and evaluated. Thermal vias and a ceramic inlay are two techniques that both meet the requirements needed for this application. Power loop layouts of a single-phase leg are then completed for these cases.
The new phase leg layouts (P2 inlay, and P2 thermal via) are compared to an existing layout, P1, using finite element analysis (FEA) to extract the loop parasitics. These are then used to perform a double pulse test simulation. A sample of the results are displayed in Fig. 2. The lower commutation loop inductances produce lower peak voltages, and less ringing in the switching transients.