Fig. 1. Hierarchical optimization process of PEBB.
In the medium-voltage power distribution system of a microgrid, power electronics converters are widely used in power source/ load center connection, current limiting and power distribution system protection. In lieu of designing power converters separately for each application, the U.S. Navy has proposed a universal power processing unit concept known as power electronics building blocks (PEBB) to be used for construction of power electronics systems of various functionalities and with different voltage and power ratings for the purpose of overall cost, loss, size and weight reduction. Consequently, it is desireable to apply optimization techniques in the design of PEBB-based power electronics systems regarding weight, size and efficiency. Fig. 1 shows the generalized hierarchical optimization procedure of PEBBs. The optimization process is devided into two levels: system level and subsystem level. The first step in system-level optimization is to specify system design requirements including system functionality, design specifications, design objectives and system design constraints. System-level optimization variables are then selected in a way that the subsystem design couplings are removed so that all subsystem-level optimizations are operated in parallel; response surfaces are generated accordingly from each subsystem-level optimization regarding all ranges of system-level optimization variable values. Metaheuristic methods assist variable value selection in both system-level and subsystem-level optimization processes for increased design efficiency and accuracy.
As a commonly encountered load type, a step load is connected to the distribution bus through a power electronics system and will cause a negative effect on the bus if its power processing stage is not carefully dealt with. In order to meet the interface standards, the optimization process of the PEBB-based power processing stage must take into account the terminal transient response performances (e.g. overshoot and settling time) as optimization design constraints. A model is constructed relating system-dynamic response with passive device selections and controller design. Two cases are plotted in Fig. 2 with different output voltage overshoot tolerance in case of a step load. As shown also in Fig. 2, terminal constraints in the system-level design are redefining the range of feasible design variable values, which again will speed up the optimization design iteration.
Fig. 2. Feasible design variable range variation with difference output voltage overshoot tolerance in case of step load.