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Design and Test of a 6 kV Phase-Leg using Four Stacked 1.7 kV SiC MOSFET High-Current Modules
Year: 2020 | Author: Keyao Sun | Paper: T5.22
Fig. 1. Experimental test-bed for eight stacked SiC MOSFET devices under test in a half-bridge configuration.
The voltage balancing method was validated with a half-bridge circuit shown in Fig. 1. For the half-bridge circuit, eight 1.7 kV rated SiC MOSFETs (four modules) were connected in series (S1 through S8). To act as a freewheeling diode, four additional modules were connected in series (D1 through D8), with each device's gate-source voltage clamped to -4 V.
Fig. 2 shows the load current Iload with all eight VDS voltages under a 6 kV dc-bus. Due to the power limitation of the dc power supply used in this experiment, a multiple-pulse test was conducted with a dc power supply, using the energy stored in the dc-bus to provide the 240 A inductive load current. Thus, the load resistor Rload, duty cycle, and switching frequency were tuned together in order to achieve 240 A switching current at 6 kV dc input and minimize the voltage drop of the dc-bus during the 8 ms test. Fig. 2 shows the balancing results and zoomed-in waveforms.
Fig. 2. Closed-loop experimental result of eight series-connected SiC MOSFETs under 6 kV bus voltage to calculate turn-off losses at 240 A (fsw = 10 kHz, D = 0.04, RLoad = 1.4W). Probes: VDS,1-6: Micsig DP20003 @ 250 MHz, VDS,7-8: Tektronix THDP0200 @ 200 MHz, ILoad: Tektronix TRCP0600 @ 500 MHz.
