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High Density Voltage Divider (2005)

Year: 2005
The two-stage VR approach was proposed by CPES to achieve high frequency and reduce output capacitance. It was demonstrated that the second stage switching frequency can be pushed to 2MHz to achieve 350kHz bandwidth and no bulk capacitors at 83% efficiency. However, Buck was traditionally used as the first stage, which is very bulky. To solve this problem, a novel ultra-high power density voltage divider with fixed conversion ratio has been proposed for the two-stage VR application. Without the magnetic component inside, its power density has been scaled up by an order over the conventional approach. The essence of the voltage divider is to run the switched capacitor circuit at a sweet point. Since the duty cycle is fixed to be 50%, all of the voltages on capacitors are near half of the input voltage. It is well known that two voltage sources can be in parallel only if the voltage of them is the same. Hence, there is no inductor needed as the buffer between the voltage sources. The proposed voltage divider can achieve ZVS turn-off and ZCS turn-on for all of the switches, so the efficiency is very high. Moreover, it also features the capability of holding ultra-high efficiency even at light load, which is promising to the battery life extension in the laptop. 2kW/inch3 power density and 98~99% efficiency have been demonstrated in 70W DC/DC prototypes designed for laptop VRs.

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