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Novel Current-Mode Digital Control Architecture (2006)

Year: 2006
Recently, digital control is gaining increasing popularity in power supplies applications. One of major challenges for digital control in high frequency applications is the quantization effects inherent in the digital control loop. A very high resolution digital pulse modulator (DWPM) is necessary to avoid unpredictable limit cycle oscillations. However, high resolution DPWM is cost prohibitive. Previously, CPES proposed several modulation methods, e.g. constant on-time modulation and nearly constant frequency modulation, which can improve the resolution of the DPWM about ten times comparing with convention DPWM methods with almost no cost impact. The fundamental issue still exists. To minimize the unwanted limit cycle oscillation, it may require a sufficient high resolution DPWM. In order to solve this issue, CPES has proposed a new digital control technique that can mitigate the need for high resolution DPWM. In this new architecture, a digital ramp is added to help improve the resolution and thus may help to circumvent the unwanted limit cycle oscillation, resulting in significant cost reduction.

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