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Solution for efficiency limitation imposed by input decoupling capacitor in non-isolated DC/DC converters (2004)

Year: 2004
Fig. 1. Comparison of 2 capacitor locations.
It was determined through simulation and then later with experimental results that the input decoupling capacitor in a synchronous DC/DC converter should be placed not next to the input voltage terminal as typically done, but rather as close to the devices as possible. As such, the parasitic inductance of the loop between the input decoupling capacitor and the two devices is reduced which has a significant positive impact on the overall efficiency of the converter.

Using a novel system design method called Stacked Power where unpackaged devices (IR DirectFETs in this case) are embedded inside a layer of aluminum nitride ceramic, the impact of this problem has been minimized. This arrangement allows for a flush top and bottom mounting so that the decoupling capacitor can be placed directly on top of the devices, effectively creating the smallest possible loop. Maxwell 3D simulations show that this design yields a 0.8nH loop inductance, which is the lowest achievable with conventional 20V devices and a 0805 ceramic capacitor since they physically cannot be closer together.

Figure 1 shows that moving the capacitor closer to the devices reduces the parasitic ringing at the switch node considerably. Even a 0.6nH inductance reduction has a significant impact. Figure 2 shows the Stacked Power module with the decoupling capacitor directly on top of the embedded switches.

This concept was demonstrated by CPES in February of 2007 and has since been adopted by Hitachi research group for use with their DrMOS, as shown at APEC in April 2008 by Dr. Hashimoto.

Fig. 2. Capacitor is directly on top of the embedded devices.

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