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Fabrication Refinements and Evaluation of a Wirebond-less Multi-Chip Power Module with 13 kV SiC MOSFETs
Year: 2023 | Author: Danielle Lester | Paper: H1.14
Fig.1. Fabrication refinements for multi-chip power modules.
Implementation of the refinements resulted in low-resistance solder bonds, planar die-attached sinter bonds, uniformly sintered substrates without warpage or cracking, and reliable connections from the substrate to the post-interconnects across every device in the MCPM. Due to the limited availability of 13kV die, a module with one die per switch position was first fabricated and characterized to verify these refinements. Fig. 2 shows waveforms during a 2.2kV, 5A double-pulse test (DPT). Even at a voltage lower than the device's maximum, initial testing shows successful fabrication by stressing the maximum device current with no bond failures. The drain-source voltage has an overshoot of 3%, achieved due to the low parasitic inductance offered by the post-interconnect module structure. The drain-source voltage rise and fall times are 130 ns and 30 ns, respectively, with a maximum dv/dt of 62 V/ns at 2.2 kV, 5 A.
