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Gate Switching Robustness and Reliability of GaN P-Gate HEMTs

Year: 2023 | Author: Bixuan Wang | Paper: H1.5
Proposed circuit
Fig. 1. Proposed circuit: (a) photo, and schematics in (b) drain-and-source grounded condition, and in (c) 400V hard-switching with inductive load condition.
  The small gate overvoltage margin is a crucial concern for the gate-driver design of gallium-nitride (GaN) Schottky-type p-gate high-electron-mobility transistors (SP-HEMTs). Previous studies on SP-HEMT gate reliability are based on DC stress or square-wave pulse I-V, with the drain and source grounded (DSG) or with a resistive load. These test conditions do not resemble device operations in inductive converters, because 1) the parasitic-induced gate ringing is usually resonance-like, and 2) high drain bias (VDC) and drain current (IDC) can concur with the gate voltage (VO) overshoot. This work develops a new circuit method, as shown in Fig. 1, to characterize the gate dynamic breakdown voltage (BVdyn) of SP-HEMTs in power converters.

  This new circuit method: 1) features a resonance-like VG overshoot with pulse width (PW) down to 20 ns; 2) can achieve the DSG condition for a direct comparison with results from the prior DC and pulse IV methods, as well as the hard switching (HSW) condition at VBUS = 400 V with an inductive load in the drain-source loop to mimic practical conditions.

  As shown in Fig. 2, at increased PW, gate BVdyn shows a decrease and then saturation at 21~22 V. Moreover, the gate BVdyn increases with temperature and is higher under hard switching than under the drain-source grounding condition. In the 400 V hard-switching condition at 150 °C, the gate BVdyn reaches 27.5 V.
Test results of gate
Fig. 2. Test results of gate BVdyn of (a) GaN SP-HEMT, and (b) Si IGBT as well as SiC MOSFET.

Such an impact from the drain-switching locus and temperature on the gate BVdyn is not seen in silicon and silicon-carbide power transistors tested in the same setup (Fig. 2). These results are explained by a decrease in the potential drop across the p-GaN gate stack in hard switching and at high temperatures.

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