High Efficiency Power Architecture (DPA) for Servers (2006)
Based on the initial study of DPS architecture and its alternatives, a promising DPA for future servers has been unveiled, as shown in below. As shown in figure, a semi-regulated bus converter (SRBC) is used to convert high voltage output from multi-channel interleaved PFC to a variable intermediate bus voltage, 5.2V~7V, for processors VRs. This low adaptive bus voltage will not greatly increase the full load efficiency of the downstream VRs, but also enhance the light load efficiency. As we know, bus converters can also achieve very high efficiency, around 96% at fixed maximum duty cycle. Moreover, during the hold-up time, the bus converter is regulated to maintain the bus voltage in the vicinity of 12V. The total server platform efficiency in this power architecture may be as high as 82%, which is about 10~15% higher than in current practice. Through this study, we are able to find a high efficiency and cost-effective structure for server application via new standardized modules.