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Design of a 24 kV PCB Based DC Bus

Year: 2022 | Author: David Nam | Paper: H-S5.2
PCB sectional view
Fig. 1. Cross-sectional view of a PCB with a high voltage layer stack up
  In this work, electric field constrained design of a 22 kV PCB-based dc bus is completed. A PCB-based dc bus allows for a high customization for high density power electronics converters, as well as minimizing parasitic inductance through deliberate design. To realize this goal, critical regions for high electric field intensity areas are defined within the board. Several steps are taken to mitigate the identified peak electric fields: methods include increasing distance between layers and staggering conducting layers. An example of such techniques can be illustrated in Fig. 1, where a cross-sectional view of a PCB that includes multiple layers at different potentials close to a through-hole via is shown. At increasing potentials, the x and y distances are increased to meet the critical peak electric field intensity requirements. Fig. 2 verifies this stack-up through finite element analysis (FEA); the white area is the peak field intensity value above the maximum allowable intensity in air. The final design of the PCB provides connections for a 22 kV rated flying capacitor inverter phase leg, while maintaining internal electric fields below the dielectric strength of the insulating material and surface electric fields below the breakdown strength of air. This design hosts multiple buses for the flying capacitor banks within one PCB, thus providing a high-density structure that can be modular. To further expand on the modularity of each phase leg, auxiliary circuit power distribution is also integrated into the PCB. Additionally, layout selection is considered to minimize total loop inductance while minimizing volume.
Simulation result
Fig. 2. Verification of high voltage PCB design through FEA simulations
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