Become a Member
Become a Member
LIBRARY
  2. Library
  3. Viewnugget
  4. 861

Phase-current Sensor and Short-circuit Detection based on Rogowski Coils Integrated with Gate Driver for 1.2 kV SiC MOSFET Half-bridge Module

Year: 2019 | Author: Slavko Mocevic | Paper: T4.6
Gate Driver Prototype
Fig. 1. Gate Driver Prototype
The necessity of having a new, fast, and reliable short-circuit protection method for SiC applications, and the emergence of high density, high efficiency trends, drove the introduction of the gate driver (GD) with an integrated Rogowski switch-current sensor (RSCS). In the newly designed GD, switch currents are measured and used for protection, while the same information is used for obtaining the phase current with a simple manipulation on the GD itself (shown on Fig. 1). Outputting the phase current from the GD is possible by knowing the switch currents in the complete switching cycle and simply subtracting these two currents. The chosen GD architecture is one where an RSCS for the top and bottom device is placed on the controller (common) ground. A digital reconstruction of the phase current is chosen, as shown in Fig. 2. The di/dt information, scaled with a factor of mutual inductance, is being con-stantly integrated by an active integrator. The output voltage of an integrator linearly represents current in the system. After buffer, there is a two-stage analog-to-digital converter (ADC) filter with a cutoff frequency of 3.3 MHz. Its main role is to filter out any high frequency ringing in the current information during switching instances. The OpAmp level shifter is employed to adjust the signal to the proper values for ADC sampling. The chosen sample rate of the ADC is 2.5 MHz in order to reduce delay of the current measurement. Two ADCs for the top and bottom switch currents are synchronized and send data in the field-programmable gate array (FPGA) at the same time instances. Immediately after successful subtraction, the FPGA starts placing that information on the digital-to-analog converter (DAC). A 2.5 Msps DAC with a small settling time, is chosen to convert information back to analog, without minimizing delay. The gate driver is able to successfully reconstruct the phase current under a dv/dt of 15 V/ns. The delay between the reconstructed phase current and the current in the system is 1.61 μs. The absolute error of the RSCS for both high and low currents is a maximum of 3 A for frequen-cies above 10 kHz. This is promising for applications with intended switching frequencies above 10 kHz and are within the silicon carbide (SiC) MOSFET domain. The reconstruction error is a maximum of 3 A for both high and low currents. The linearity error is 2.5 %. A fast detection time of 80 ns for short-circuit events, and a reaction time of 200 ns are achieved; both limit overheat-ing and stresses in the module. The total time spent in protecting the short-circuit is around 1.2 μs, minimizing overshoot and thermal stresses.
Digital phase current reconstruction principle.
Fig. 2. Digital phase current reconstruction principle.
Return to CPES Showcase

Our Industry Partners

About CPES

Events/Presentations

Education

Interested in Becoming a CPES Member?

Learn more


Having technical issues?

Get Help

Copyright © 2021 Virginia Tech Center for Power Electronics Systems