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Degradation of SiC MOSFETs Provoked by a Switching Based Ruggedness Test
Year: 2020 | Author: Joseph Kozak | Paper: T1.8
Fig. 1. ALT electrical stress conditions with relation to the SOA (top) and experimental switching cycling IV locus (bottom).
The objective of switching cycling is to observe the degradation of the semiconductor through repetitive hard switching events. Two independent degradation and failure mechanisms have been identified. While the gate-oxide degradation emerges with the increased switching cycles, bulk-semiconductor degradation appears simultaneously and drives the device into a partially failed‐yet functional‐state before failure. Changes in electrical parameters over time, including threshold voltage on-resistance, gate-leakage, and drain leakage currents are all monitored, and precursors for two degrada- tion mechanisms have been identified. Fig. 2(a) shows the changes in drain leakage for device D4, and Fig. 2(b) depicts the gate leakage currents over time for all devices.
Fig. 2. Changes in (a) drain leakage current of device D4 and (b) changes in gate leakage current of all devices.
