Modeling and Control for 48V/1V Sigma Converter
Fig. 1 shows the bode plot of constant-on-time current mode and enhanced V2 control, as well as the comparison with voltage mode control, where Vin=54V, Vo=1.4V, D=0.07, n=12, Lr=440nH, L=210nH, Cin=10uF, Co=2mF. From Fig. 1, voltage mode has a low frequency double pole and COT current mode has a low frequency RHP pole (Gain decreases and phase increases). As a result, both voltage mode and COT current mode are not suitable for high-bandwidth design and enhanced V2 control is chosen.
It is well known that CPU VR must achieve adaptive voltage positioning (AVP) to meet Intel load line specification. In order to meet the AVP requirement, the active droop control scheme is adopted as shown in Fig. 2. With this method, constant load line is achieved at all operating regions.